Merry
1e35b99f74
AInstEmitSimdCvt: Half-precision to single-precision conversion ( #235 )
2018-07-12 15:51:02 -03:00
gdkchan
c590201b2a
Fix ZIP/UZP/TRN instructions when Rd == Rn || Rd == Rm ( #239 )
2018-07-09 22:48:28 -03:00
gdkchan
0daf70a1d9
Query multiple pages at once with GetWriteWatch ( #222 )
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* Query multiple pages at once with GetWriteWatch
* Allow multiple buffer types to share the same page, aways use the physical address as cache key
* Remove a variable that is no longer needed
2018-07-08 16:55:15 -03:00
Merry
a47b96571e
ChocolArm64: More accurate implementation of Frecpe & Frecps ( #228 )
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* ChocolArm64: More accurate implementation of Frecpe
* ChocolArm64: Handle infinities and zeros in Frecps
2018-07-08 16:54:47 -03:00
Merry
666e7e2e4c
ASoftFloat: Fix InvSqrtEstimate for negative values ( #233 )
2018-07-08 12:41:46 -03:00
gdkchan
8aee846940
Remove broken adds/cmn with condition check optimization ( #218 )
2018-07-03 21:54:05 -03:00
gdkchan
392c5b7d98
Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions ( #200 )
2018-07-03 03:31:48 -03:00
LDj3SNuD
8d7582a918
Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. ( #212 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdLogical.cs
* Update AVectorHelper.cs
* Update ASoftFallback.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Improve CountSetBits8() algorithm.
* Improve CountSetBits8() algorithm.
2018-07-03 03:31:16 -03:00
Thomas Guillemard
051740f344
Add linux-x64 to RID property to make tests works on linux ( #205 )
2018-06-30 12:43:04 -03:00
LDj3SNuD
ac5c1e5107
Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. ( #204 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update Instructions.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-06-30 12:40:41 -03:00
gdkchan
7e59d1b639
Add Sse2 fallback to Vector{Extract|Insert}Single methods on the CPU ( #193 )
2018-06-28 20:52:32 -03:00
gdkchan
f58651d009
Add support for the FMLA (by element/scalar) instruction ( #187 )
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* Add support for the FMLA (by element/scalar) instruction
* Fix encoding
2018-06-28 20:51:38 -03:00
gdkchan
a12f31867c
Implement SvcGetThreadContext3
2018-06-26 01:10:15 -03:00
LDj3SNuD
31871077e2
Add Sqxtun_S, Sqxtun_V with 3 tests. ( #188 )
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* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
2018-06-25 23:36:20 -03:00
LDj3SNuD
86aae79b9d
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. ( #183 )
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* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 22:32:29 -03:00
gdkchan
216bcd7a65
Add REV16/32 (vector) instructions and fix REV64
2018-06-25 18:40:55 -03:00
Rygnus
3f81e1c795
Add opcodes SQXTUN_S and SQXTUN_V ( #184 )
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* Add SQXTUN_S and SQXTUN_V
Part 1/2 of commit
* Add SQXTUN_S and SQXTUN_V (2/2)
Part 2/2 of commit
2018-06-25 14:23:46 -03:00
gdkchan
c9813159d1
Small OpenGL Renderer refactoring ( #177 )
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* Call OpenGL functions directly, remove the pfifo thread, some refactoring
* Fix PerformanceStatistics calculating the wrong host fps, remove wait event on PFIFO as this wasn't exactly was causing the freezes (may replace with an exception later)
* Organized the Gpu folder a bit more, renamed a few things, address PR feedback
* Make PerformanceStatistics thread safe
* Remove unused constant
* Use unlimited update rate for better pref
2018-06-23 21:39:25 -03:00
gdkchan
f6ff678834
Fix some thread sync issues ( #172 )
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* Fix some thread sync issues
* Remove some debug stuff
* Ensure that writes to the mutex address clears the exclusive monitor
2018-06-21 23:05:42 -03:00
riperiperi
32900cc223
Rework signed multiplication. Fixed an edge case and passes all tests. ( #174 )
2018-06-20 10:45:20 -03:00
LDj3SNuD
7084bf58a4
Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmtst_S compare instructions. Add 22 compare tests (Scalar, Vector). Add Eor_V, Not_V tests. ( #171 )
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* Add files via upload
* Add files via upload
* Delete CpuTestScalar.cs
* Update CpuTestSimdArithmetic.cs
2018-06-18 14:55:26 -03:00
gdkchan
ed80772500
Add the FADDP (scalar) instruction
2018-06-18 00:41:28 -03:00
riperiperi
05ef572474
Faster soft implementation of smulh and umulh ( #134 )
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* Faster soft implementation of smulh and umulh
* smulh: Fixed mul with 0 acting like it had a negative result.
* Use compliment for negative smulh result.
2018-06-13 10:55:45 -03:00
Lordmau5
d99c39b448
Implement Fabs_V ( #146 )
2018-06-12 09:29:16 -03:00
gdkchan
231539a9e8
Move WriteBytes to AMemory, implement it with a Marshal copy like ReadBytes, fix regression on address range checking
2018-06-09 13:05:41 -03:00
gdkchan
0e8fd39636
Small cleanup in AMemory and removed some unused usings
2018-06-08 23:54:50 -03:00
gdkchan
1743dde334
Do not inline the scalar vector load methods as a workaround to a .net JIT bug
2018-06-08 23:49:53 -03:00
gdkchan
eafe47fee0
Texture/Vertex/Index data cache ( #132 )
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* Initial implementation of the texture cache
* Cache vertex and index data aswell, some cleanup
* Improve handling of the cache by storing cached ranges on a list for each page
* Delete old data from the caches automatically, ensure that the cache is cleaned when the mapping/size changes, and some general cleanup
2018-06-08 21:15:56 -03:00
riperiperi
81b59077f8
ReadBytes function in AMemory, with cleaner range check. ( #136 )
2018-06-08 21:15:02 -03:00
gdkchan
f1027d5511
Force inline some of the vector read/write methods
2018-06-04 16:11:11 -03:00
gdkchan
65f781ae7b
Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code
2018-06-02 11:44:52 -03:00
gdkchan
7869b7e257
Added support for more shader instructions and texture formats, fix swapped channels in RGB565 and RGBA5551? texture formats, allow zero values on blending registers, initial work to build CFG on the shader decoder, update the BRA instruction to work with it (WIP)
2018-05-29 20:37:10 -03:00
gdkchan
09b194aaf0
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
2018-05-26 17:50:47 -03:00
gdkchan
d29632d7de
Fix wrong type on CMTST instruction
2018-05-23 12:57:28 -03:00
gdkchan
e54a0ff9c6
Remove some calls generated on the CPU for inexistent intrinsic methods
2018-05-23 00:27:48 -03:00
gdkchan
173c3e616d
Add scalar variants of FCVTZS/FCVTZU, fix a issue on Ryushader
2018-05-18 14:44:49 -03:00
gdkchan
1aa96453ef
Add intrinsics support ( #121 )
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* Initial intrinsics support
* Update tests to work with the new Vector128 type and intrinsics
* Drop SSE4.1 requirement
* Fix copy-paste mistake
2018-05-11 20:10:27 -03:00
gdkchan
428360c5ac
NvServices refactoring ( #120 )
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* Initial implementation of NvMap/NvHostCtrl
* More work on NvHostCtrl
* Refactoring of nvservices, move GPU Vmm, make Vmm per-process, refactor most gpu devices, move Gpu to Core, fix CbBind
* Implement GetGpuTime, support CancelSynchronization, fix issue on InsertWaitingMutex, proper double buffering support (again, not working properly for commercial games, only hb)
* Try to fix perf regression reading/writing textures, moved syncpts and events to a UserCtx class, delete global state when the process exits, other minor tweaks
* Remove now unused code, add comment about probably wrong result codes
2018-05-07 15:53:23 -03:00
LDj3SNuD
f9b17f86c1
Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). ( #110 )
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* Update ILGeneratorEx.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
2018-04-29 20:39:58 -03:00
LDj3SNuD
3f3844583f
Update AOpCodeTable.cs ( #108 )
2018-04-25 23:26:41 -03:00
LDj3SNuD
966f6b7203
Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. ( #104 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdLogical.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
2018-04-25 23:20:22 -03:00
gdkchan
27ed5ed039
Improved logging ( #103 )
2018-04-24 15:57:39 -03:00
gdkchan
d45a67fd36
Print guest stack trace on a few points that can throw exceptions
2018-04-22 02:48:17 -03:00
gdkchan
28f7c6decf
Stub a few services, add support for generating call stacks on the CPU
2018-04-22 01:22:46 -03:00
LDj3SNuD
9c43b14421
Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. ( #96 )
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* Update AOpCodeTable.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update Instructions.cs
* Revert "Started to work in improving the sync primitives"
2018-04-21 16:15:04 -03:00
LDj3SNuD
bc4ada20c7
Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. ( #92 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update Bits.cs
* Create CpuTestSimd.cs
* Create CpuTestSimdReg.cs
* Update CpuTestSimd.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update CpuTestSimdReg.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-04-20 12:40:15 -03:00
gdkchan
76c1d1440c
Add SvcSetThreadActivity, tweak SignalProcessWideKey, add fmul32i shader instructions and other small fixes
2018-04-19 16:18:30 -03:00
MS-DOS1999
b0368079fb
Fix Fmin/max and add vector version, add and modifying fmin/max tests ( #89 )
2018-04-19 00:22:12 -03:00
LDj3SNuD
5a383d86b1
Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. ( #88 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AOpCodeTable.cs
2018-04-18 10:56:27 -03:00
LDj3SNuD
16660f177e
Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). ( #77 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
2018-04-12 11:52:00 -03:00