Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
* Update AOpCodeTable.cs * Update AInstEmitSimdShift.cs * Update CpuTestSimdShImm.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Create CpuTestSimdIns.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
This commit is contained in:
LDj3SNuD
gdkchan
parent
80836050ef
commit
3d16dbe12c
4 changed files with 207 additions and 106 deletions
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@ -364,6 +364,7 @@ namespace ChocolArm64
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SetA64("0x00111000100000000110xxxxxxxxxx", AInstEmit.Rev16_V, typeof(AOpCodeSimd));
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SetA64("0x1011100x100000000010xxxxxxxxxx", AInstEmit.Rev32_V, typeof(AOpCodeSimd));
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SetA64("0x001110<<100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
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SetA64("0x00111100>>>xxx100011xxxxxxxxxx", AInstEmit.Rshrn_V, typeof(AOpCodeSimdShImm));
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SetA64("0x101110<<1xxxxx011000xxxxxxxxxx", AInstEmit.Rsubhn_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011111xxxxxxxxxx", AInstEmit.Saba_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Sabal_V, typeof(AOpCodeSimdReg));
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@ -409,7 +410,14 @@ namespace ChocolArm64
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SetA64("01111110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg));
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SetA64("0x101110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("0101111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_S, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_V, typeof(AOpCodeSimdShImm));
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SetA64("0111111100>>>xxx100011xxxxxxxxxx", AInstEmit.Sqrshrun_S, typeof(AOpCodeSimdShImm));
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SetA64("0x10111100>>>xxx100011xxxxxxxxxx", AInstEmit.Sqrshrun_V, typeof(AOpCodeSimdShImm));
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SetA64("0101111100>>>xxx100101xxxxxxxxxx", AInstEmit.Sqshrn_S, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx100101xxxxxxxxxx", AInstEmit.Sqshrn_V, typeof(AOpCodeSimdShImm));
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SetA64("0111111100>>>xxx100001xxxxxxxxxx", AInstEmit.Sqshrun_S, typeof(AOpCodeSimdShImm));
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SetA64("0x10111100>>>xxx100001xxxxxxxxxx", AInstEmit.Sqshrun_V, typeof(AOpCodeSimdShImm));
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SetA64("01011110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_S, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_V, typeof(AOpCodeSimdReg));
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SetA64("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd));
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@ -476,6 +484,10 @@ namespace ChocolArm64
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SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V, typeof(AOpCodeSimdReg));
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SetA64("01111110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Uqadd_S, typeof(AOpCodeSimdReg));
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SetA64("0>101110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Uqadd_V, typeof(AOpCodeSimdReg));
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SetA64("0111111100>>>xxx100111xxxxxxxxxx", AInstEmit.Uqrshrn_S, typeof(AOpCodeSimdShImm));
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SetA64("0x10111100>>>xxx100111xxxxxxxxxx", AInstEmit.Uqrshrn_V, typeof(AOpCodeSimdShImm));
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SetA64("0111111100>>>xxx100101xxxxxxxxxx", AInstEmit.Uqshrn_S, typeof(AOpCodeSimdShImm));
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SetA64("0x10111100>>>xxx100101xxxxxxxxxx", AInstEmit.Uqshrn_V, typeof(AOpCodeSimdShImm));
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SetA64("01111110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_S, typeof(AOpCodeSimdReg));
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SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_V, typeof(AOpCodeSimdReg));
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SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
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@ -1199,22 +1199,22 @@ namespace ChocolArm64.Instruction
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public static void Sqxtn_S(AILEmitterCtx Context)
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{
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EmitScalarSaturatingNarrowOpSxSx(Context, () => { });
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EmitSaturatingNarrowOp(Context, SaturatingNarrowFlags.ScalarSxSx);
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}
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public static void Sqxtn_V(AILEmitterCtx Context)
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{
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EmitVectorSaturatingNarrowOpSxSx(Context, () => { });
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EmitSaturatingNarrowOp(Context, SaturatingNarrowFlags.VectorSxSx);
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}
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public static void Sqxtun_S(AILEmitterCtx Context)
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{
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EmitScalarSaturatingNarrowOpSxZx(Context, () => { });
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EmitSaturatingNarrowOp(Context, SaturatingNarrowFlags.ScalarSxZx);
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}
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public static void Sqxtun_V(AILEmitterCtx Context)
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{
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EmitVectorSaturatingNarrowOpSxZx(Context, () => { });
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EmitSaturatingNarrowOp(Context, SaturatingNarrowFlags.VectorSxZx);
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}
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public static void Srhadd_V(AILEmitterCtx Context)
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@ -1455,12 +1455,12 @@ namespace ChocolArm64.Instruction
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public static void Uqxtn_S(AILEmitterCtx Context)
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{
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EmitScalarSaturatingNarrowOpZxZx(Context, () => { });
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EmitSaturatingNarrowOp(Context, SaturatingNarrowFlags.ScalarZxZx);
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}
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public static void Uqxtn_V(AILEmitterCtx Context)
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{
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EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
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EmitSaturatingNarrowOp(Context, SaturatingNarrowFlags.VectorZxZx);
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}
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public static void Urhadd_V(AILEmitterCtx Context)
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@ -1004,56 +1004,14 @@ namespace ChocolArm64.Instruction
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ScalarSxSx = Scalar | SignedSrc | SignedDst,
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ScalarSxZx = Scalar | SignedSrc,
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ScalarZxSx = Scalar | SignedDst,
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ScalarZxZx = Scalar,
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VectorSxSx = SignedSrc | SignedDst,
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VectorSxZx = SignedSrc,
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VectorZxSx = SignedDst,
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VectorZxZx = 0
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}
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public static void EmitScalarSaturatingNarrowOpSxSx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.ScalarSxSx);
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}
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public static void EmitScalarSaturatingNarrowOpSxZx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.ScalarSxZx);
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}
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public static void EmitScalarSaturatingNarrowOpZxSx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.ScalarZxSx);
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}
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public static void EmitScalarSaturatingNarrowOpZxZx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.ScalarZxZx);
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}
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public static void EmitVectorSaturatingNarrowOpSxSx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.VectorSxSx);
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}
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public static void EmitVectorSaturatingNarrowOpSxZx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.VectorSxZx);
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}
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public static void EmitVectorSaturatingNarrowOpZxSx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.VectorZxSx);
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}
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public static void EmitVectorSaturatingNarrowOpZxZx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.VectorZxZx);
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}
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public static void EmitSaturatingNarrowOp(AILEmitterCtx Context, Action Emit, SaturatingNarrowFlags Flags)
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public static void EmitSaturatingNarrowOp(AILEmitterCtx Context, SaturatingNarrowFlags Flags)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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@ -1080,8 +1038,6 @@ namespace ChocolArm64.Instruction
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
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Emit();
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EmitSatQ(Context, Op.Size, SignedSrc, SignedDst);
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EmitVectorInsertTmp(Context, Part + Index, Op.Size);
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@ -10,6 +10,11 @@ namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Rshrn_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmNarrowOpZx(Context, Round: true);
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}
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public static void Shl_S(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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@ -45,9 +50,7 @@ namespace ChocolArm64.Instruction
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public static void Shrn_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmNarrowBinaryZx(Context, () => Context.Emit(OpCodes.Shr_Un), GetImmShr(Op));
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EmitVectorShrImmNarrowOpZx(Context, Round: false);
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}
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public static void Sli_V(AILEmitterCtx Context)
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@ -85,26 +88,44 @@ namespace ChocolArm64.Instruction
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}
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}
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public static void Sqrshrn_S(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxSx);
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}
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public static void Sqrshrn_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxSx);
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}
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int Shift = GetImmShr(Op);
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long RoundConst = 1L << (Shift - 1);
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Action Emit = () =>
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public static void Sqrshrun_S(AILEmitterCtx Context)
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{
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Context.EmitLdc_I8(RoundConst);
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxZx);
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}
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Context.Emit(OpCodes.Add);
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public static void Sqrshrun_V(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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}
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Context.EmitLdc_I4(Shift);
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public static void Sqshrn_S(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxSx);
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}
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Context.Emit(OpCodes.Shr);
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};
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public static void Sqshrn_V(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxSx);
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}
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EmitVectorSaturatingNarrowOpSxSx(Context, Emit);
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public static void Sqshrun_S(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxZx);
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}
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public static void Sqshrun_V(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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}
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public static void Srshr_S(AILEmitterCtx Context)
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@ -159,6 +180,26 @@ namespace ChocolArm64.Instruction
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Accumulate);
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}
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public static void Uqrshrn_S(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarZxZx);
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}
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public static void Uqrshrn_V(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorZxZx);
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}
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public static void Uqshrn_S(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarZxZx);
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}
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public static void Uqshrn_V(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorZxZx);
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}
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public static void Urshr_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Round);
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@ -367,6 +408,138 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitVectorShrImmNarrowOpZx(AILEmitterCtx Context, bool Round)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = GetImmShr(Op);
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long RoundConst = 1L << (Shift - 1);
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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if (Part != 0)
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{
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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}
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
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if (Round)
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{
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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}
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Context.EmitLdc_I4(Shift);
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Context.Emit(OpCodes.Shr_Un);
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EmitVectorInsertTmp(Context, Part + Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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[Flags]
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private enum ShrImmSaturatingNarrowFlags
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{
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Scalar = 1 << 0,
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SignedSrc = 1 << 1,
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SignedDst = 1 << 2,
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Round = 1 << 3,
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ScalarSxSx = Scalar | SignedSrc | SignedDst,
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ScalarSxZx = Scalar | SignedSrc,
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ScalarZxZx = Scalar,
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VectorSxSx = SignedSrc | SignedDst,
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VectorSxZx = SignedSrc,
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VectorZxZx = 0
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}
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private static void EmitRoundShrImmSaturatingNarrowOp(AILEmitterCtx Context, ShrImmSaturatingNarrowFlags Flags)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.Round | Flags);
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}
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private static void EmitShrImmSaturatingNarrowOp(AILEmitterCtx Context, ShrImmSaturatingNarrowFlags Flags)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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bool Scalar = (Flags & ShrImmSaturatingNarrowFlags.Scalar) != 0;
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bool SignedSrc = (Flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0;
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bool SignedDst = (Flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0;
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bool Round = (Flags & ShrImmSaturatingNarrowFlags.Round) != 0;
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int Shift = GetImmShr(Op);
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long RoundConst = 1L << (Shift - 1);
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int Elems = !Scalar ? 8 >> Op.Size : 1;
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int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
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if (Scalar)
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{
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EmitVectorZeroLowerTmp(Context);
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}
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if (Part != 0)
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{
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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}
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
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if (Op.Size <= 1 || !Round)
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{
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if (Round)
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{
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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}
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Context.EmitLdc_I4(Shift);
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Context.Emit(SignedSrc ? OpCodes.Shr : OpCodes.Shr_Un);
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}
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else /* if (Op.Size == 2 && Round) */
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{
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EmitShrImm_64(Context, SignedSrc, RoundConst, Shift); // Shift <= 32
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}
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EmitSatQ(Context, Op.Size, SignedSrc, SignedDst);
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EmitVectorInsertTmp(Context, Part + Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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// Dst_64 = (Int(Src_64, Signed) + RoundConst) >> Shift;
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private static void EmitShrImm_64(
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AILEmitterCtx Context,
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@ -374,11 +547,6 @@ namespace ChocolArm64.Instruction
|
|||
long RoundConst,
|
||||
int Shift)
|
||||
{
|
||||
if (((AOpCodeSimd)Context.CurrOp).Size < 3)
|
||||
{
|
||||
throw new InvalidOperationException();
|
||||
}
|
||||
|
||||
Context.EmitLdc_I8(RoundConst);
|
||||
Context.EmitLdc_I4(Shift);
|
||||
|
||||
|
|
@ -387,41 +555,6 @@ namespace ChocolArm64.Instruction
|
|||
: nameof(ASoftFallback.UnsignedShrImm_64));
|
||||
}
|
||||
|
||||
private static void EmitVectorShImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
||||
{
|
||||
EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, true);
|
||||
}
|
||||
|
||||
private static void EmitVectorShImmNarrowBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
|
||||
{
|
||||
EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, false);
|
||||
}
|
||||
|
||||
private static void EmitVectorShImmNarrowBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
|
||||
{
|
||||
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
||||
|
||||
int Elems = 8 >> Op.Size;
|
||||
|
||||
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
||||
|
||||
for (int Index = 0; Index < Elems; Index++)
|
||||
{
|
||||
EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed);
|
||||
|
||||
Context.EmitLdc_I4(Imm);
|
||||
|
||||
Emit();
|
||||
|
||||
EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
|
||||
}
|
||||
|
||||
if (Part == 0)
|
||||
{
|
||||
EmitVectorZeroUpper(Context, Op.Rd);
|
||||
}
|
||||
}
|
||||
|
||||
private static void EmitVectorShImmWidenBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
||||
{
|
||||
EmitVectorShImmWidenBinaryOp(Context, Emit, Imm, true);
|
||||
|
|
|
|||
Loading…
Reference in a new issue