Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
* Update AOpCodeTable.cs * Update AInstEmitSimdShift.cs * Update ASoftFallback.cs * Update AOpCodeSimdShImm.cs * Update ABitUtils.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Create CpuTestSimdShImm.cs * Create CpuTestSimdRegElem.cs * Address PR feedback. * Nit. * Nit.
This commit is contained in:
LDj3SNuD
gdkchan
parent
1be39f720f
commit
80836050ef
7 changed files with 255 additions and 98 deletions
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@ -27,6 +27,10 @@ namespace ChocolArm64
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return -1;
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}
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private static readonly sbyte[] HbsNibbleTbl = { -1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 };
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public static int HighestBitSetNibble(int Value) => HbsNibbleTbl[Value & 0b1111];
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public static long Replicate(long Bits, int Size)
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{
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long Output = 0;
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@ -54,4 +58,4 @@ namespace ChocolArm64
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return Value != 0 && (Value & (Value - 1)) == 0;
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}
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}
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}
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}
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@ -343,6 +343,7 @@ namespace ChocolArm64
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SetA64("0x001110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mla_V, typeof(AOpCodeSimdReg));
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SetA64("0x101111xxxxxxxx0000x0xxxxxxxxxx", AInstEmit.Mla_Ve, typeof(AOpCodeSimdRegElem));
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SetA64("0x101110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mls_V, typeof(AOpCodeSimdReg));
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SetA64("0x101111xxxxxxxx0100x0xxxxxxxxxx", AInstEmit.Mls_Ve, typeof(AOpCodeSimdRegElem));
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SetA64("0x00111100000xxx0xx001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
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SetA64("0x00111100000xxx10x001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
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SetA64("0x00111100000xxx110x01xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
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@ -380,8 +381,9 @@ namespace ChocolArm64
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SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V, typeof(AOpCodeSimd));
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SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Shadd_V, typeof(AOpCodeSimdReg));
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SetA64("010111110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm));
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SetA64("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
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SetA64("0101111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
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SetA64("0100111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
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SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V, typeof(AOpCodeSimd));
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SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm));
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SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Shsub_V, typeof(AOpCodeSimdReg));
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@ -415,13 +417,18 @@ namespace ChocolArm64
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SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd));
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SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd));
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SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Srhadd_V, typeof(AOpCodeSimdReg));
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SetA64("0101111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_S, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0101111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_S, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm));
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SetA64("0100111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm));
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SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
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SetA64("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
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SetA64("0101111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0100111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0101111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_S, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
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SetA64("0100111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
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SetA64("0x001110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Ssubl_V, typeof(AOpCodeSimdReg));
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@ -474,6 +481,12 @@ namespace ChocolArm64
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SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
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SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V, typeof(AOpCodeSimd));
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SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Urhadd_V, typeof(AOpCodeSimdReg));
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SetA64("0111111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_S, typeof(AOpCodeSimdShImm));
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SetA64("0x10111100>>>xxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0110111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0111111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_S, typeof(AOpCodeSimdShImm));
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SetA64("0x10111100>>>xxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm));
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SetA64("0110111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm));
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SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg));
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SetA64("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V, typeof(AOpCodeSimdShImm));
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SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm));
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@ -481,6 +494,7 @@ namespace ChocolArm64
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SetA64("0110111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm));
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SetA64("01111110xx100000001110xxxxxxxxxx", AInstEmit.Usqadd_S, typeof(AOpCodeSimd));
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SetA64("0>101110<<100000001110xxxxxxxxxx", AInstEmit.Usqadd_V, typeof(AOpCodeSimd));
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SetA64("0111111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_S, typeof(AOpCodeSimdShImm));
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SetA64("0x10111100>>>xxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
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SetA64("0110111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
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SetA64("0x101110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Usubl_V, typeof(AOpCodeSimdReg));
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@ -10,7 +10,7 @@ namespace ChocolArm64.Decoder
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{
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Imm = (OpCode >> 16) & 0x7f;
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Size = ABitUtils.HighestBitSet32(Imm >> 3);
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Size = ABitUtils.HighestBitSetNibble(Imm >> 3);
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}
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}
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}
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}
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@ -957,6 +957,15 @@ namespace ChocolArm64.Instruction
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});
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}
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public static void Mls_Ve(AILEmitterCtx Context)
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{
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EmitVectorTernaryOpByElemZx(Context, () =>
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{
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Context.Emit(OpCodes.Mul);
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Context.Emit(OpCodes.Sub);
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});
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}
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public static void Mul_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
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@ -626,6 +626,9 @@ namespace ChocolArm64.Instruction
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed);
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Context.EmitSttmp();
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for (int Index = 0; Index < Elems; Index++)
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{
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if (Ternary)
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@ -634,7 +637,7 @@ namespace ChocolArm64.Instruction
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}
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed);
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Context.EmitLdtmp();
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Emit();
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@ -14,20 +14,24 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, 0, Op.Size);
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EmitScalarUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.Emit(OpCodes.Shl);
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EmitScalarSet(Context, Op.Rd, Op.Size);
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Context.Emit(OpCodes.Shl);
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});
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}
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public static void Shl_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
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EmitVectorUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.Emit(OpCodes.Shl);
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});
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}
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public static void Shll_V(AILEmitterCtx Context)
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@ -103,15 +107,24 @@ namespace ChocolArm64.Instruction
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EmitVectorSaturatingNarrowOpSxSx(Context, Emit);
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}
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public static void Srshr_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Round);
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}
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public static void Srshr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Round);
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}
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int Shift = GetImmShr(Op);
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public static void Srsra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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long RoundConst = 1L << (Shift - 1);
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EmitVectorRoundShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift, RoundConst);
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public static void Srsra_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Sshl_V(AILEmitterCtx Context)
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@ -128,35 +141,42 @@ namespace ChocolArm64.Instruction
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public static void Sshr_S(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorExtractSx(Context, Op.Rn, 0, Op.Size);
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr);
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EmitScalarSet(Context, Op.Rd, Op.Size);
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EmitShrImmOp(Context, ShrImmFlags.ScalarSx);
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}
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public static void Sshr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitShrImmOp(Context, ShrImmFlags.VectorSx);
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}
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EmitVectorShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), GetImmShr(Op));
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public static void Ssra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Accumulate);
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}
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public static void Ssra_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Accumulate);
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}
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Action Emit = () =>
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{
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Context.Emit(OpCodes.Shr);
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Context.Emit(OpCodes.Add);
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};
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public static void Urshr_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Round);
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}
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EmitVectorShImmTernarySx(Context, Emit, GetImmShr(Op));
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public static void Urshr_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Round);
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}
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public static void Ursra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Ursra_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Ushl_V(AILEmitterCtx Context)
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@ -173,41 +193,22 @@ namespace ChocolArm64.Instruction
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public static void Ushr_S(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitScalarUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr_Un);
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});
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EmitShrImmOp(Context, ShrImmFlags.ScalarZx);
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}
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public static void Ushr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitShrImmOp(Context, ShrImmFlags.VectorZx);
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}
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EmitVectorUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr_Un);
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});
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public static void Usra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Accumulate);
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}
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public static void Usra_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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Action Emit = () =>
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{
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr_Un);
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Context.Emit(OpCodes.Add);
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};
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EmitVectorOp(Context, Emit, OperFlags.RdRn, Signed: false);
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Accumulate);
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}
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private static void EmitVectorShl(AILEmitterCtx Context, bool Signed)
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@ -274,78 +275,118 @@ namespace ChocolArm64.Instruction
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}
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[Flags]
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private enum ShImmFlags
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private enum ShrImmFlags
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{
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None = 0,
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Scalar = 1 << 0,
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Signed = 1 << 1,
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Signed = 1 << 0,
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Ternary = 1 << 1,
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Rounded = 1 << 2,
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Round = 1 << 2,
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Accumulate = 1 << 3,
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SignedTernary = Signed | Ternary,
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SignedRounded = Signed | Rounded
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ScalarSx = Scalar | Signed,
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ScalarZx = Scalar,
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VectorSx = Signed,
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VectorZx = 0
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}
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private static void EmitVectorShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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private static void EmitScalarShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.Signed);
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EmitShrImmOp(Context, ShrImmFlags.ScalarSx | Flags);
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}
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private static void EmitVectorShImmTernarySx(AILEmitterCtx Context, Action Emit, int Imm)
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private static void EmitScalarShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedTernary);
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EmitShrImmOp(Context, ShrImmFlags.ScalarZx | Flags);
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}
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private static void EmitVectorShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
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private static void EmitVectorShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.None);
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EmitShrImmOp(Context, ShrImmFlags.VectorSx | Flags);
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}
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private static void EmitVectorRoundShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm, long Rc)
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private static void EmitVectorShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedRounded, Rc);
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EmitShrImmOp(Context, ShrImmFlags.VectorZx | Flags);
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}
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private static void EmitVectorShImmOp(AILEmitterCtx Context, Action Emit, int Imm, ShImmFlags Flags, long Rc = 0)
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private static void EmitShrImmOp(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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bool Scalar = (Flags & ShrImmFlags.Scalar) != 0;
|
||||
bool Signed = (Flags & ShrImmFlags.Signed) != 0;
|
||||
bool Round = (Flags & ShrImmFlags.Round) != 0;
|
||||
bool Accumulate = (Flags & ShrImmFlags.Accumulate) != 0;
|
||||
|
||||
int Shift = GetImmShr(Op);
|
||||
|
||||
long RoundConst = 1L << (Shift - 1);
|
||||
|
||||
int Bytes = Op.GetBitsCount() >> 3;
|
||||
int Elems = Bytes >> Op.Size;
|
||||
|
||||
bool Signed = (Flags & ShImmFlags.Signed) != 0;
|
||||
bool Ternary = (Flags & ShImmFlags.Ternary) != 0;
|
||||
bool Rounded = (Flags & ShImmFlags.Rounded) != 0;
|
||||
int Elems = !Scalar ? Bytes >> Op.Size : 1;
|
||||
|
||||
for (int Index = 0; Index < Elems; Index++)
|
||||
{
|
||||
if (Ternary)
|
||||
{
|
||||
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
|
||||
}
|
||||
|
||||
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
|
||||
|
||||
if (Rounded)
|
||||
if (Op.Size <= 2)
|
||||
{
|
||||
Context.EmitLdc_I8(Rc);
|
||||
if (Round)
|
||||
{
|
||||
Context.EmitLdc_I8(RoundConst);
|
||||
|
||||
Context.Emit(OpCodes.Add);
|
||||
}
|
||||
|
||||
Context.EmitLdc_I4(Shift);
|
||||
|
||||
Context.Emit(Signed ? OpCodes.Shr : OpCodes.Shr_Un);
|
||||
}
|
||||
else /* if (Op.Size == 3) */
|
||||
{
|
||||
EmitShrImm_64(Context, Signed, Round ? RoundConst : 0L, Shift);
|
||||
}
|
||||
|
||||
if (Accumulate)
|
||||
{
|
||||
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
|
||||
|
||||
Context.Emit(OpCodes.Add);
|
||||
}
|
||||
|
||||
Context.EmitLdc_I4(Imm);
|
||||
|
||||
Emit();
|
||||
|
||||
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
|
||||
EmitVectorInsertTmp(Context, Index, Op.Size);
|
||||
}
|
||||
|
||||
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
||||
Context.EmitLdvectmp();
|
||||
Context.EmitStvec(Op.Rd);
|
||||
|
||||
if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar)
|
||||
{
|
||||
EmitVectorZeroUpper(Context, Op.Rd);
|
||||
}
|
||||
}
|
||||
|
||||
// Dst_64 = (Int(Src_64, Signed) + RoundConst) >> Shift;
|
||||
private static void EmitShrImm_64(
|
||||
AILEmitterCtx Context,
|
||||
bool Signed,
|
||||
long RoundConst,
|
||||
int Shift)
|
||||
{
|
||||
if (((AOpCodeSimd)Context.CurrOp).Size < 3)
|
||||
{
|
||||
throw new InvalidOperationException();
|
||||
}
|
||||
|
||||
Context.EmitLdc_I8(RoundConst);
|
||||
Context.EmitLdc_I4(Shift);
|
||||
|
||||
ASoftFallback.EmitCall(Context, Signed
|
||||
? nameof(ASoftFallback.SignedShrImm_64)
|
||||
: nameof(ASoftFallback.UnsignedShrImm_64));
|
||||
}
|
||||
|
||||
private static void EmitVectorShImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
||||
{
|
||||
EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, true);
|
||||
|
|
@ -414,4 +455,4 @@ namespace ChocolArm64.Instruction
|
|||
Context.EmitStvec(Op.Rd);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,6 +16,92 @@ namespace ChocolArm64.Instruction
|
|||
Context.EmitCall(typeof(ASoftFallback), MthdName);
|
||||
}
|
||||
|
||||
#region "ShrImm_64"
|
||||
public static long SignedShrImm_64(long Value, long RoundConst, int Shift)
|
||||
{
|
||||
if (RoundConst == 0L)
|
||||
{
|
||||
if (Shift <= 63)
|
||||
{
|
||||
return Value >> Shift;
|
||||
}
|
||||
else /* if (Shift == 64) */
|
||||
{
|
||||
if (Value < 0L)
|
||||
{
|
||||
return -1L;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0L;
|
||||
}
|
||||
}
|
||||
}
|
||||
else /* if (RoundConst == 1L << (Shift - 1)) */
|
||||
{
|
||||
if (Shift <= 63)
|
||||
{
|
||||
long Add = Value + RoundConst;
|
||||
|
||||
if ((~Value & (Value ^ Add)) < 0L)
|
||||
{
|
||||
return (long)((ulong)Add >> Shift);
|
||||
}
|
||||
else
|
||||
{
|
||||
return Add >> Shift;
|
||||
}
|
||||
}
|
||||
else /* if (Shift == 64) */
|
||||
{
|
||||
return 0L;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
public static ulong UnsignedShrImm_64(ulong Value, long RoundConst, int Shift)
|
||||
{
|
||||
if (RoundConst == 0L)
|
||||
{
|
||||
if (Shift <= 63)
|
||||
{
|
||||
return Value >> Shift;
|
||||
}
|
||||
else /* if (Shift == 64) */
|
||||
{
|
||||
return 0UL;
|
||||
}
|
||||
}
|
||||
else /* if (RoundConst == 1L << (Shift - 1)) */
|
||||
{
|
||||
ulong Add = Value + (ulong)RoundConst;
|
||||
|
||||
if ((Add < Value) && (Add < (ulong)RoundConst))
|
||||
{
|
||||
if (Shift <= 63)
|
||||
{
|
||||
return (Add >> Shift) | (0x8000000000000000UL >> (Shift - 1));
|
||||
}
|
||||
else /* if (Shift == 64) */
|
||||
{
|
||||
return 1UL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (Shift <= 63)
|
||||
{
|
||||
return Add >> Shift;
|
||||
}
|
||||
else /* if (Shift == 64) */
|
||||
{
|
||||
return 0UL;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "Saturating"
|
||||
public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue