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Ryujinx-git/Ryujinx.Tests/Cpu/Tester
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LDj3SNuD fa5545aab8 Implement Ssubw_V and Usubw_V instructions. (#287) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdHelper.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdMove.cs

* Update AInstEmitSimdCmp.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs
2018-07-18 21:06:28 -03:00
..
Types Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. (#92) 2018-04-20 12:40:15 -03:00
Instructions.cs Implement Ssubw_V and Usubw_V instructions. (#287) 2018-07-18 21:06:28 -03:00
Pseudocode.cs Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) 2018-06-25 22:32:29 -03:00