3bdd109f45
* Add files via upload * Add files via upload * Delete CpuTestScalar.cs * Update CpuTestSimdArithmetic.cs
163 lines
8.1 KiB
C#
163 lines
8.1 KiB
C#
//#define CcmpReg
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("CcmpReg"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestCcmpReg : CpuTest
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{
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#if CcmpReg
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[SetUp]
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public void SetupTester()
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{
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AArch64.TakeReset(false);
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}
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[Test, Description("CCMN <Xn>, <Xm>, #<nzcv>, <cond>")]
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public void Ccmn_64bit([Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
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[Random(0u, 15u, 1)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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uint Opcode = 0xBA400000; // CCMN X0, X0, #0, EQ
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5);
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Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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AArch64.X((int)Rm, new Bits(Xm));
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Base.Ccmn_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
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Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
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Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
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Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
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});
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}
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[Test, Description("CCMN <Wn>, <Wm>, #<nzcv>, <cond>")]
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public void Ccmn_32bit([Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
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[Random(0u, 15u, 1)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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uint Opcode = 0x3A400000; // CCMN W0, W0, #0, EQ
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5);
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Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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AArch64.X((int)Rm, new Bits(Wm));
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Base.Ccmn_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
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Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
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Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
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Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
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});
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}
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[Test, Description("CCMP <Xn>, <Xm>, #<nzcv>, <cond>")]
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public void Ccmp_64bit([Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
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[Random(0u, 15u, 1)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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uint Opcode = 0xFA400000; // CCMP X0, X0, #0, EQ
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5);
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Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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AArch64.X((int)Rm, new Bits(Xm));
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Base.Ccmp_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
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Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
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Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
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Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
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});
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}
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[Test, Description("CCMP <Wn>, <Wm>, #<nzcv>, <cond>")]
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public void Ccmp_32bit([Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
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[Random(0u, 15u, 1)] uint nzcv,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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uint Opcode = 0x7A400000; // CCMP W0, W0, #0, EQ
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5);
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Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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AArch64.X((int)Rm, new Bits(Wm));
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Base.Ccmp_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
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Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
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Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
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Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
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});
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}
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#endif
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}
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}
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