3 commits

Author	SHA1	Message	Date
gdkchan	7c314eadcf	Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)	2018-02-15 01:32:25 -03:00
gdkchan	55743c0cba	Only throw undefined instruction exception at execution, not at translation stage	2018-02-10 14:20:46 -03:00
gdkchan	6a3aa6cd88	Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions	2018-02-09 00:26:20 -03:00

Renamed from Ryujinx/Cpu/Decoder/AOpCodeSimdMemMult.cs (Browse further)