gdkchan
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1c44d9f66d
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Fix for some SIMD issues
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2018-02-18 01:57:33 -03:00 |
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gdkchan
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595e7ee588
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Add FCVTAS and FCVTAU instructions
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2018-02-17 18:59:37 -03:00 |
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gdkchan
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161193e113
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CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements
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2018-02-17 18:06:11 -03:00 |
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gdkchan
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7c314eadcf
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Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)
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2018-02-15 01:32:25 -03:00 |
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gdkchan
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7ed1153062
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Add SHRN instruction, and fix ADDV
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2018-02-14 02:43:21 -03:00 |
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gdkchan
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7d11a146c0
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Generate CIL for SCVTF (vector), add undefined encodings for some instructions
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2018-02-12 00:37:20 -03:00 |
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gdkchan
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9f612682e0
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Add BRK on the opcode table
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2018-02-10 12:16:48 -03:00 |
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gdkchan
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ccc9ce1908
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Move a few more SIMD instructions to emit CIL directly instead of a method call
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2018-02-09 17:14:47 -03:00 |
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gdkchan
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6a3aa6cd88
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Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions
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2018-02-09 00:26:20 -03:00 |
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gdkchan
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d0954564cd
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Add ADC and SBC instructions
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2018-02-07 20:46:36 -03:00 |
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gdkchan
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79f028e410
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Add FMADD and FMSUB instructions
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2018-02-07 20:07:16 -03:00 |
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gdkchan
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768b573772
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Add FMOV (scalar, register) and FCMPE instructions
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2018-02-07 19:43:52 -03:00 |
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gdkchan
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d77d691381
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Implement SSHL instruction, fix exception on FMAX/FMIN, and use a better exception message for undefined/unimplemented instructions
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2018-02-07 09:38:43 -03:00 |
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gdkchan
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b7e1d9930d
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aloha
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2018-02-04 20:08:20 -03:00 |
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