From bc26aa558a500a07ded8e3f32f5b26fe19794ad2 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Thu, 28 Jun 2018 20:51:38 -0300
Subject: [PATCH] Add support for the FMLA (by element/scalar) instruction
 (#187)

* Add support for the FMLA (by element/scalar) instruction

* Fix encoding
---
 ChocolArm64/AOpCodeTable.cs                        | 1 +
 ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs | 9 +++++++++
 ChocolArm64/Instruction/AInstEmitSimdHelper.cs     | 7 +++++++
 3 files changed, 17 insertions(+)

diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs
index e78d0b57..1f60be1c 100644
--- a/ChocolArm64/AOpCodeTable.cs
+++ b/ChocolArm64/AOpCodeTable.cs
@@ -271,6 +271,7 @@ namespace ChocolArm64
             SetA64("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S,        typeof(AOpCodeSimdReg));
             SetA64("0x0011101x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V,        typeof(AOpCodeSimdReg));
             SetA64("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S,      typeof(AOpCodeSimdReg));
+            SetA64("010111111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Se,       typeof(AOpCodeSimdRegElemF));
             SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V,        typeof(AOpCodeSimdReg));
             SetA64("0x0011111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Ve,       typeof(AOpCodeSimdRegElemF));
             SetA64("0>0011101<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmls_V,        typeof(AOpCodeSimdReg));
diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index 14dbf1d6..efd3cc6e 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -516,6 +516,15 @@ namespace ChocolArm64.Instruction
             Fmin_S(Context);
         }
 
+        public static void Fmla_Se(AILEmitterCtx Context)
+        {
+            EmitScalarTernaryOpByElemF(Context, () =>
+            {
+                Context.Emit(OpCodes.Mul);
+                Context.Emit(OpCodes.Add);
+            });
+        }
+
         public static void Fmla_V(AILEmitterCtx Context)
         {
             EmitVectorTernaryOpF(Context, () =>
diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
index 80c6aeb7..bca45649 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
@@ -260,6 +260,13 @@ namespace ChocolArm64.Instruction
             EmitScalarOpByElemF(Context, Emit, Op.Index, Ternary: false);
         }
 
+        public static void EmitScalarTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
+        {
+            AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
+
+            EmitScalarOpByElemF(Context, Emit, Op.Index, Ternary: true);
+        }
+
         public static void EmitScalarOpByElemF(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary)
         {
             AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;