T32: Implement ALU (shifted register) instructions (#3135)
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)
* OpCodeTable: Sort T32 list
* Tests: Rename RandomTestCase to PrecomputedThumbTestCase
* T32: Tests for AluRsImm instructions
* fix nit
* fix nit 2
2022-02-22 22:11:28 +00:00
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namespace ARMeilleure.Decoders
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{
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class OpCodeT32 : OpCode32
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{
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32(inst, address, opCode);
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public OpCodeT32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Cond = Condition.Al;
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2022-09-11 02:03:14 +00:00
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IsThumb = true;
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T32: Implement ALU (shifted register) instructions (#3135)
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)
* OpCodeTable: Sort T32 list
* Tests: Rename RandomTestCase to PrecomputedThumbTestCase
* T32: Tests for AluRsImm instructions
* fix nit
* fix nit 2
2022-02-22 22:11:28 +00:00
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OpCodeSizeInBytes = 4;
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}
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}
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}
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