ryujinx-archive/ChocolArm64
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54 commits

Author SHA1 Message Date
LDj3SNuD
966f6b7203 Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdLogical.cs

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs
 2018-04-25 23:20:22 -03:00
gdkchan
27ed5ed039 Improved logging (#103) 2018-04-24 15:57:39 -03:00
gdkchan
d45a67fd36 Print guest stack trace on a few points that can throw exceptions 2018-04-22 02:48:17 -03:00
gdkchan
28f7c6decf Stub a few services, add support for generating call stacks on the CPU 2018-04-22 01:22:46 -03:00
LDj3SNuD
bc4ada20c7 Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. (#92) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update Bits.cs

* Create CpuTestSimd.cs

* Create CpuTestSimdReg.cs

* Update CpuTestSimd.cs

Provide a better supply of input values for the 20 Simd Tests.

* Update CpuTestSimdReg.cs

Provide a better supply of input values for the 20 Simd Tests.

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs
 2018-04-20 12:40:15 -03:00
MS-DOS1999
b0368079fb Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89) 2018-04-19 00:22:12 -03:00
LDj3SNuD
5a383d86b1 Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. (#88) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AOpCodeTable.cs
 2018-04-18 10:56:27 -03:00
LDj3SNuD
16660f177e Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdMove.cs

* Update CpuTestSimdMove.cs

* Update AInstEmitSimdMove.cs

* Update CpuTestSimdMove.cs
 2018-04-12 11:52:00 -03:00
gdkchan
2afc12c4a7 [CPU] Fix CNT instruction 2018-04-10 20:58:32 -03:00
LDj3SNuD
65c490f350 Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Update CpuTestSimdArithmetic.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs
 2018-04-08 16:08:57 -03:00
gdkchan
137eb89fad [CPU] Fail early when the index/size of the vector is invalid 2018-04-06 15:39:39 -03:00
gdkchan
6282fe6607 Fix FRSQRTS and FCM* (scalar) instructions 2018-04-06 10:20:17 -03:00
gdkchan
35ff142104 Add FMLS (vector) instruction 2018-04-06 01:41:54 -03:00
gdkchan
b73b522835 Add FRSQRTS and FCM* instructions 2018-04-05 23:28:12 -03:00
Merry
c4c247deb4 Implement Frsqrte_S (#72) 
* Implement Frsqrte_S

* Implement Frsqrte_V

* Add Frsqrte_S test
 2018-04-05 20:36:19 -03:00
gdkchan
ee98d50e17 Add Faddp (vector) instruction 2018-04-04 22:13:10 -03:00
gdkchan
9037055c10 Add FNEG (vector) instruction 2018-04-04 16:36:07 -03:00
gdkchan
6cb940049d Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction) 2018-03-30 17:37:31 -03:00
gdkchan
94b3eb96a9 Add BIT instruction 2018-03-30 16:46:00 -03:00
gdkchan
e580ef1bcf Add UABD instruction 2018-03-30 16:30:23 -03:00
gdkchan
7423ff43a5 Add UABDL instruction 2018-03-30 16:16:16 -03:00
gdkchan
442904a5ed Add UADDL instruction 2018-03-30 15:55:28 -03:00
gdkchan
0a7aaa345c Add UHADD instruction 2018-03-30 12:37:07 -03:00
gdkchan
4f92aa0ee2 Add FNMADD instruction 2018-03-24 00:28:23 -03:00
LDj3SNuD
eca2d19d8d Add Cls Instruction. (#67) 
* Update AInstEmitAlu.cs

* Update ASoftFallback.cs

* Update AOpCodeTable.cs
 2018-03-23 22:06:05 -03:00
MS-DOS1999
9e124e75f4 Add Frint Instructions and Tests (#62) 
* add 'ADC 32bit and Overflow' test

* Add WZR/WSP tests

* fix ADC and ADDS

* add ADCS test

* add SBCS test

* indent my code and delete comment

* '/' <- i hate you x)

* remove spacebar char

* remove false tab

* add frintx_S test

* update frintx_S test

* add ASRV test

* fix new line

* fix PR

* fix indent

* Add add_V tests

* work on Frintx_V

* Add Frintx_V Instruction

* add some instruction and test

* Syntax + indent

* Delete Console Write

* Delete Console Write 2

* CR del

* Skip NaNs tests

* Skip NaNs tests 2

* Fix errors 1

* Fix errors 2
 2018-03-23 07:40:23 -03:00
gdkchan
c8cd538f15 Add BFI instruction, even more audout fixes 2018-03-16 00:42:44 -03:00
gdkchan
f4f5d244f1 Add MLA (vector by element), fixes some cases of MUL (vector by element)? 2018-03-15 22:36:47 -03:00
gdkchan
70f8db413b Fix crc32 instruction with size greater than a byte 2018-03-15 18:14:22 -03:00
gdkchan
bcf4cbf135 CPU fix for the cases using a Mask with shift = 0 2018-03-14 01:59:22 -03:00
gdkchan
d3ec30ec32 Remove unused function from CPU 2018-03-14 00:57:07 -03:00
gdkchan
bb0a2aa0f1 Add CRC32 instruction and SLI (vector) 2018-03-14 00:12:05 -03:00
gdkchan
25d8e7e733 Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count 2018-03-13 21:24:32 -03:00
gdkchan
67bd1505df IAudioDeviceService -> IAudioDevice 2018-03-12 16:31:09 -03:00
gdkchan
bb1c0b23a3 Fix GetAudioRenderersProcessMasterVolume which was totally wrong 2018-03-12 16:29:06 -03:00
gdkchan
ca13db7d84 Allow more than one process, free resources on process dispose, implement SvcExitThread 2018-03-12 01:14:12 -03:00
gdkchan
d986ef7e86 Allow to enable/disable memory checks even on release mode through the flag, return error for invalid addresses on SvcMap*Memory svcs, do not return error on SvcQueryMemory (instead, return reserved for the end of the address space), other minor tweaks 2018-03-10 20:39:16 -03:00
gdkchan
f43e430f6c Fix EmitScalarUnaryOpF and add SSRA (vector) 2018-03-10 00:00:31 -03:00
gdkchan
4f9faf3e32 Add FRINTM (vector) instruction 2018-03-09 23:41:05 -03:00
gdkchan
e182fb74f2 Add SHLL instruction 2018-03-09 23:28:38 -03:00
gdkchan
9376a61229 Add SMLAL (vector), fix EXT instruction 2018-03-06 21:36:49 -03:00
gdkchan
3020de224e Add MUL (vector by element), fix FCVTN, make svcs use MakeError too 2018-03-05 16:18:37 -03:00
gdkchan
3860ba6521 Add FCVTL and FCVTN instruction (no Half support yet), stub SvcClearEvent 2018-03-05 12:58:56 -03:00
gdkchan
6d60fcfc24 Improve CPU initial translation speeds (#50) 
* Add background translation to the CPU

* Do not use a separate thread for translation, implement 2 tiers translation

* Remove unnecessary usings

* Lower MinCallCountForReJit

* Remove unused variable
 2018-03-04 14:09:59 -03:00
gdkchan
6dd9cdf337 Fix REV64 (vector) instruction 2018-03-02 20:24:16 -03:00
gdkchan
589d90785a Add REV64 (vector) instruction 2018-03-02 20:03:28 -03:00
gdkchan
fc105218a2 Add EXT, CMTST (vector) and UMULL (vector) instructions 2018-03-02 19:23:38 -03:00
gdkchan
1cb0bbe585 Fix corner cases of ADCS and SBFM 2018-02-26 15:56:34 -03:00
gdkchan
068754fec5 Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store 2018-02-25 22:14:58 -03:00
gdkchan
d2f3bd3526 Add FABD (scalar), ADCS, SBCS instructions, update config with better default control mappings, update readme with the new mappings 2018-02-24 18:47:08 -03:00