Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110)
* Update ILGeneratorEx.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update Pseudocode.cs * Update Instructions.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdArithmetic.cs
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3 changed files with 104 additions and 2 deletions
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@ -337,6 +337,8 @@ namespace ChocolArm64
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Set("0x001110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Smin_V, typeof(AOpCodeSimdReg));
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Set("0x001110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Smlal_V, typeof(AOpCodeSimdReg));
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Set("0x001110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Smull_V, typeof(AOpCodeSimdReg));
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Set("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd));
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Set("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V, typeof(AOpCodeSimd));
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Set("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
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Set("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
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Set("010111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
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@ -370,6 +372,8 @@ namespace ChocolArm64
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Set("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V, typeof(AOpCodeSimdReg));
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Set("0x001110000xxxxx001111xxxxxxxxxx", AInstEmit.Umov_S, typeof(AOpCodeSimdIns));
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Set("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V, typeof(AOpCodeSimdReg));
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Set("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
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Set("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V, typeof(AOpCodeSimd));
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Set("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg));
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Set("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V, typeof(AOpCodeSimdShImm));
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Set("011111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm));
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@ -205,6 +205,84 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitQxtn(AILEmitterCtx Context, bool Signed, bool Scalar)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = (!Scalar ? 8 >> Op.Size : 1);
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int ESize = 8 << Op.Size;
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int TMaxValue = (Signed ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
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int TMinValue = (Signed ? -((1 << (ESize - 1))) : 0);
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int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0);
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Context.EmitLdc_I8(0L);
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Context.EmitSttmp();
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for (int Index = 0; Index < Elems; Index++)
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{
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AILLabel LblLe = new AILLabel();
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AILLabel LblGeEnd = new AILLabel();
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I4(TMaxValue);
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Context.Emit(OpCodes.Conv_U8);
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Context.Emit(Signed ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
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Context.Emit(OpCodes.Pop);
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Context.EmitLdc_I4(TMaxValue);
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Context.EmitLdc_I8(0x8000000L);
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Context.EmitSttmp();
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Context.Emit(OpCodes.Br_S, LblGeEnd);
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Context.MarkLabel(LblLe);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I4(TMinValue);
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Context.Emit(OpCodes.Conv_I8);
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Context.Emit(Signed ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
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Context.Emit(OpCodes.Pop);
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Context.EmitLdc_I4(TMinValue);
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Context.EmitLdc_I8(0x8000000L);
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Context.EmitSttmp();
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Context.MarkLabel(LblGeEnd);
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if (Scalar)
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{
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EmitVectorZeroLower(Context, Op.Rd);
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}
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EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
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}
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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Context.EmitLdtmp();
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Context.Emit(OpCodes.Conv_I4);
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Context.Emit(OpCodes.Or);
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Context.EmitCallPropSet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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}
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public static void Fabd_S(AILEmitterCtx Context)
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{
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EmitScalarBinaryOpF(Context, () =>
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@ -971,6 +1049,16 @@ namespace ChocolArm64.Instruction
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EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Mul));
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}
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public static void Sqxtn_S(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: true, Scalar: true);
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}
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public static void Sqxtn_V(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: true, Scalar: false);
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}
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public static void Sub_S(AILEmitterCtx Context)
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{
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EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
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@ -1049,5 +1137,15 @@ namespace ChocolArm64.Instruction
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{
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
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}
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public static void Uqxtn_S(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: false, Scalar: true);
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}
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public static void Uqxtn_V(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: false, Scalar: false);
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}
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}
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}
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