ryujinx-archive/ChocolArm64
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Fix 32-bits extended register instructions with 64-bits extensions

Browse source
This commit is contained in:
gdkchan 2018-03-30 23:32:06 -03:00
parent 67184bcff7
commit ce9ccfd1cc
1 changed files with 11 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
Translation/AILEmitterCtx.cs
View file

@ -72,7 +72,7 @@ namespace ChocolArm64.Translation
Emitter = new AILEmitter(Graph, Root, SubName); Emitter = new AILEmitter(Graph, Root, SubName);
ILBlock = Emitter.GetILBlock(0); ILBlock = Emitter.GetILBlock(0);
OpcIndex = -1; OpcIndex = -1;
@ -260,18 +260,24 @@ namespace ChocolArm64.Translation
case AIntType.Int64: Emit(OpCodes.Conv_I8); break; case AIntType.Int64: Emit(OpCodes.Conv_I8); break;
} }
if (IntType == AIntType.UInt64 || bool Sz64 = CurrOp.RegisterSize != ARegisterSize.Int32;
IntType == AIntType.Int64)
if (Sz64 == (IntType == AIntType.UInt64 ||
IntType == AIntType.Int64))
{ {
return; return;
} }
if (CurrOp.RegisterSize != ARegisterSize.Int32) if (Sz64)
{ {
Emit(IntType >= AIntType.Int8 Emit(IntType >= AIntType.Int8
? OpCodes.Conv_I8 ? OpCodes.Conv_I8
: OpCodes.Conv_U8); : OpCodes.Conv_U8);
} }
else
{
Emit(OpCodes.Conv_U4);
}
} }
public void EmitLsl(int Amount) => EmitILShift(Amount, OpCodes.Shl); public void EmitLsl(int Amount) => EmitILShift(Amount, OpCodes.Shl);
@ -298,7 +304,7 @@ namespace ChocolArm64.Translation
EmitLdc_I4(Amount); EmitLdc_I4(Amount);
Emit(OpCodes.Shr_Un); Emit(OpCodes.Shr_Un);
Ldloc(Tmp2Index, AIoType.Int); Ldloc(Tmp2Index, AIoType.Int);
EmitLdc_I4(CurrOp.GetBitsCount() - Amount); EmitLdc_I4(CurrOp.GetBitsCount() - Amount);