Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. (#204)
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update Instructions.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
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7e59d1b639
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3 changed files with 101 additions and 27 deletions
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@ -352,6 +352,10 @@ namespace ChocolArm64
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SetA64("0x1011100x100000000010xxxxxxxxxx", AInstEmit.Rev32_V, typeof(AOpCodeSimd));
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SetA64("0x1011100x100000000010xxxxxxxxxx", AInstEmit.Rev32_V, typeof(AOpCodeSimd));
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SetA64("0x001110<<100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
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SetA64("0x001110<<100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
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SetA64("0x101110<<1xxxxx011000xxxxxxxxxx", AInstEmit.Rsubhn_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011000xxxxxxxxxx", AInstEmit.Rsubhn_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011111xxxxxxxxxx", AInstEmit.Saba_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Sabal_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Sabd_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Sabdl_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
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SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
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SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
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SetA64("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));
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SetA64("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));
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@ -390,6 +394,8 @@ namespace ChocolArm64
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SetA64("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl));
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SetA64("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl));
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SetA64("0>001110<<0xxxxx001010xxxxxxxxxx", AInstEmit.Trn1_V, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<0xxxxx001010xxxxxxxxxx", AInstEmit.Trn1_V, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<0xxxxx011010xxxxxxxxxx", AInstEmit.Trn2_V, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<0xxxxx011010xxxxxxxxxx", AInstEmit.Trn2_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011111xxxxxxxxxx", AInstEmit.Uaba_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Uabal_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Uabd_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Uabd_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg));
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@ -22,19 +22,6 @@ namespace ChocolArm64.Instruction
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EmitVectorUnaryOpSx(Context, () => EmitAbs(Context));
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EmitVectorUnaryOpSx(Context, () => EmitAbs(Context));
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}
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}
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private static void EmitAbs(AILEmitterCtx Context)
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{
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AILLabel LblTrue = new AILLabel();
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Context.Emit(OpCodes.Dup);
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Context.Emit(OpCodes.Ldc_I4_0);
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Context.Emit(OpCodes.Bge_S, LblTrue);
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Context.Emit(OpCodes.Neg);
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Context.MarkLabel(LblTrue);
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}
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public static void Add_S(AILEmitterCtx Context)
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public static void Add_S(AILEmitterCtx Context)
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{
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{
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EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
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EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
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@ -179,6 +166,19 @@ namespace ChocolArm64.Instruction
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}
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}
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}
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}
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private static void EmitAbs(AILEmitterCtx Context)
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{
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AILLabel LblTrue = new AILLabel();
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Context.Emit(OpCodes.Dup);
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Context.Emit(OpCodes.Ldc_I4_0);
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Context.Emit(OpCodes.Bge_S, LblTrue);
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Context.Emit(OpCodes.Neg);
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Context.MarkLabel(LblTrue);
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}
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private static void EmitHighNarrow(AILEmitterCtx Context, Action Emit, bool Round)
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private static void EmitHighNarrow(AILEmitterCtx Context, Action Emit, bool Round)
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{
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -188,6 +188,8 @@ namespace ChocolArm64.Instruction
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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long RoundConst = 1L << (ESize - 1);
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for (int Index = 0; Index < Elems; Index++)
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for (int Index = 0; Index < Elems; Index++)
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{
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
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@ -197,7 +199,7 @@ namespace ChocolArm64.Instruction
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if (Round)
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if (Round)
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{
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{
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Context.EmitLdc_I8(1L << (ESize - 1));
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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Context.Emit(OpCodes.Add);
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}
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}
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@ -220,11 +222,11 @@ namespace ChocolArm64.Instruction
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int Elems = (!Scalar ? 8 >> Op.Size : 1);
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int Elems = (!Scalar ? 8 >> Op.Size : 1);
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int ESize = 8 << Op.Size;
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int ESize = 8 << Op.Size;
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int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0);
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int TMaxValue = (SignedDst ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
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int TMaxValue = (SignedDst ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
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int TMinValue = (SignedDst ? -((1 << (ESize - 1))) : 0);
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int TMinValue = (SignedDst ? -((1 << (ESize - 1))) : 0);
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int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0);
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Context.EmitLdc_I8(0L);
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Context.EmitLdc_I8(0L);
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Context.EmitSttmp();
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Context.EmitSttmp();
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@ -1107,6 +1109,46 @@ namespace ChocolArm64.Instruction
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EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), Round: true);
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EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), Round: true);
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}
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}
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public static void Saba_V(AILEmitterCtx Context)
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{
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EmitVectorTernaryOpSx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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EmitAbs(Context);
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Context.Emit(OpCodes.Add);
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});
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}
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public static void Sabal_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmTernaryOpSx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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EmitAbs(Context);
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Context.Emit(OpCodes.Add);
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});
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}
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public static void Sabd_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpSx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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EmitAbs(Context);
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});
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}
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public static void Sabdl_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmBinaryOpSx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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EmitAbs(Context);
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});
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}
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public static void Saddw_V(AILEmitterCtx Context)
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public static void Saddw_V(AILEmitterCtx Context)
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{
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{
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EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
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EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
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@ -1186,23 +1228,44 @@ namespace ChocolArm64.Instruction
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EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), Round: false);
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EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), Round: false);
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}
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}
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public static void Uaba_V(AILEmitterCtx Context)
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{
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EmitVectorTernaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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EmitAbs(Context);
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Context.Emit(OpCodes.Add);
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});
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}
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public static void Uabal_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmTernaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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EmitAbs(Context);
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Context.Emit(OpCodes.Add);
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});
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}
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public static void Uabd_V(AILEmitterCtx Context)
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public static void Uabd_V(AILEmitterCtx Context)
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{
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{
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EmitVectorBinaryOpZx(Context, () => EmitAbd(Context));
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EmitVectorBinaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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EmitAbs(Context);
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});
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}
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}
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public static void Uabdl_V(AILEmitterCtx Context)
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public static void Uabdl_V(AILEmitterCtx Context)
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{
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{
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EmitVectorWidenRnRmBinaryOpZx(Context, () => EmitAbd(Context));
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EmitVectorWidenRnRmBinaryOpZx(Context, () =>
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}
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private static void EmitAbd(AILEmitterCtx Context)
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{
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{
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Context.Emit(OpCodes.Sub);
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Context.Emit(OpCodes.Sub);
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EmitAbs(Context);
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Type[] Types = new Type[] { typeof(long) };
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});
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Context.EmitCall(typeof(Math).GetMethod(nameof(Math.Abs), Types));
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}
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}
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public static void Uaddl_V(AILEmitterCtx Context)
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public static void Uaddl_V(AILEmitterCtx Context)
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@ -483,6 +483,11 @@ namespace ChocolArm64.Instruction
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EmitVectorOp(Context, Emit, OperFlags.RnRm, true);
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EmitVectorOp(Context, Emit, OperFlags.RnRm, true);
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}
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}
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public static void EmitVectorTernaryOpSx(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorOp(Context, Emit, OperFlags.RdRnRm, true);
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}
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public static void EmitVectorUnaryOpZx(AILEmitterCtx Context, Action Emit)
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public static void EmitVectorUnaryOpZx(AILEmitterCtx Context, Action Emit)
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{
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{
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EmitVectorOp(Context, Emit, OperFlags.Rn, false);
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EmitVectorOp(Context, Emit, OperFlags.Rn, false);
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