diff --git a/AOpCodeTable.cs b/AOpCodeTable.cs index 4dc1575..71a179d 100644 --- a/AOpCodeTable.cs +++ b/AOpCodeTable.cs @@ -148,6 +148,8 @@ namespace ChocolArm64 Set("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V, typeof(AOpCodeSimdReg)); Set("0x101110101xxxxx000111xxxxxxxxxx", AInstEmit.Bit_V, typeof(AOpCodeSimdReg)); Set("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V, typeof(AOpCodeSimdReg)); + Set("0x001110<<100000010010xxxxxxxxxx", AInstEmit.Cls_V, typeof(AOpCodeSimd)); + Set("0x101110<<100000010010xxxxxxxxxx", AInstEmit.Clz_V, typeof(AOpCodeSimd)); Set("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg)); Set("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd)); Set("0>001110<<1xxxxx001111xxxxxxxxxx", AInstEmit.Cmge_V, typeof(AOpCodeSimdReg)); @@ -289,6 +291,7 @@ namespace ChocolArm64 Set("0111111011100000101110xxxxxxxxxx", AInstEmit.Neg_S, typeof(AOpCodeSimd)); Set("0>101110<<100000101110xxxxxxxxxx", AInstEmit.Neg_V, typeof(AOpCodeSimd)); Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd)); + Set("0x001110111xxxxx000111xxxxxxxxxx", AInstEmit.Orn_V, typeof(AOpCodeSimdReg)); Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg)); Set("0x00111100000xxx< Context.EmitCall(MthdInfo)); + } + + public static void Clz_V(AILEmitterCtx Context) + { + MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingZeros)); + + EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo)); + } + + private static void EmitCountLeadingBits(AILEmitterCtx Context, Action Emit) + { + AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + + int Bytes = Context.CurrOp.GetBitsCount() >> 3; + + for (int Index = 0; Index < (Bytes >> Op.Size); Index++) + { + EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size); + + Context.EmitLdc_I4(8 << Op.Size); + + Emit(); + + EmitVectorInsert(Context, Op.Rd, Index, Op.Size); + } + + if (Op.RegisterSize == ARegisterSize.SIMD64) + { + EmitVectorZeroUpper(Context, Op.Rd); + } + } + public static void Cnt_V(AILEmitterCtx Context) { AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; diff --git a/Instruction/AInstEmitSimdLogical.cs b/Instruction/AInstEmitSimdLogical.cs index 967c3d3..25aa873 100644 --- a/Instruction/AInstEmitSimdLogical.cs +++ b/Instruction/AInstEmitSimdLogical.cs @@ -103,6 +103,15 @@ namespace ChocolArm64.Instruction EmitVectorUnaryOpZx(Context, () => Context.Emit(OpCodes.Not)); } + public static void Orn_V(AILEmitterCtx Context) + { + EmitVectorBinaryOpZx(Context, () => + { + Context.Emit(OpCodes.Not); + Context.Emit(OpCodes.Or); + }); + } + public static void Orr_V(AILEmitterCtx Context) { EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Or)); @@ -136,4 +145,4 @@ namespace ChocolArm64.Instruction } } } -} \ No newline at end of file +} diff --git a/Instruction/ASoftFallback.cs b/Instruction/ASoftFallback.cs index c08f253..497605a 100644 --- a/Instruction/ASoftFallback.cs +++ b/Instruction/ASoftFallback.cs @@ -20,18 +20,12 @@ namespace ChocolArm64.Instruction Context.EmitCall(typeof(ASoftFallback), MthdName); } - public static uint CountLeadingSigns32(uint Value) => (uint)CountLeadingSigns(Value, 32); - public static ulong CountLeadingSigns64(ulong Value) => (ulong)CountLeadingSigns(Value, 64); - - private static ulong CountLeadingSigns(ulong Value, int Size) + public static ulong CountLeadingSigns(ulong Value, int Size) { return CountLeadingZeros((Value >> 1) ^ Value, Size - 1); } - public static uint CountLeadingZeros32(uint Value) => (uint)CountLeadingZeros(Value, 32); - public static ulong CountLeadingZeros64(ulong Value) => (ulong)CountLeadingZeros(Value, 64); - - private static ulong CountLeadingZeros(ulong Value, int Size) + public static ulong CountLeadingZeros(ulong Value, int Size) { int HighBit = Size - 1;