Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions (#200)
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8d7582a918
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4 changed files with 106 additions and 31 deletions
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@ -367,7 +367,9 @@ namespace ChocolArm64
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SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm));
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SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Sli_V, typeof(AOpCodeSimdShImm));
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SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Sli_V, typeof(AOpCodeSimdShImm));
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SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Smaxp_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Smin_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Smin_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx101011xxxxxxxxxx", AInstEmit.Sminp_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Smlal_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Smlal_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Smull_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Smull_V, typeof(AOpCodeSimdReg));
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SetA64("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd));
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SetA64("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd));
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@ -407,6 +409,10 @@ namespace ChocolArm64
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SetA64("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S, typeof(AOpCodeSimd));
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SetA64("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S, typeof(AOpCodeSimd));
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SetA64("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V, typeof(AOpCodeSimd));
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SetA64("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V, typeof(AOpCodeSimd));
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SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Umax_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Umaxp_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Umin_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx101011xxxxxxxxxx", AInstEmit.Uminp_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110000xxxxx001111xxxxxxxxxx", AInstEmit.Umov_S, typeof(AOpCodeSimdIns));
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SetA64("0x001110000xxxxx001111xxxxxxxxxx", AInstEmit.Umov_S, typeof(AOpCodeSimdIns));
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SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V, typeof(AOpCodeSimdReg));
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SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
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SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
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@ -58,32 +58,7 @@ namespace ChocolArm64.Instruction
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public static void Addp_V(AILEmitterCtx Context)
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public static void Addp_V(AILEmitterCtx Context)
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{
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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EmitVectorPairwiseOpZx(Context, () => Context.Emit(OpCodes.Add));
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Half = Elems >> 1;
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for (int Index = 0; Index < Elems; Index++)
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{
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int Elem = (Index & (Half - 1)) << 1;
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EmitVectorExtractZx(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 0, Op.Size);
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EmitVectorExtractZx(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 1, Op.Size);
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Context.Emit(OpCodes.Add);
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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}
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public static void Addv_V(AILEmitterCtx Context)
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public static void Addv_V(AILEmitterCtx Context)
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@ -1163,6 +1138,15 @@ namespace ChocolArm64.Instruction
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EmitVectorBinaryOpSx(Context, () => Context.EmitCall(MthdInfo));
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EmitVectorBinaryOpSx(Context, () => Context.EmitCall(MthdInfo));
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}
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}
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public static void Smaxp_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(long), typeof(long) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Max), Types);
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EmitVectorPairwiseOpSx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Smin_V(AILEmitterCtx Context)
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public static void Smin_V(AILEmitterCtx Context)
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{
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{
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Type[] Types = new Type[] { typeof(long), typeof(long) };
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Type[] Types = new Type[] { typeof(long), typeof(long) };
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@ -1172,6 +1156,15 @@ namespace ChocolArm64.Instruction
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EmitVectorBinaryOpSx(Context, () => Context.EmitCall(MthdInfo));
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EmitVectorBinaryOpSx(Context, () => Context.EmitCall(MthdInfo));
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}
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}
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public static void Sminp_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(long), typeof(long) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
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EmitVectorPairwiseOpSx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Smlal_V(AILEmitterCtx Context)
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public static void Smlal_V(AILEmitterCtx Context)
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{
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{
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EmitVectorWidenRnRmTernaryOpSx(Context, () =>
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EmitVectorWidenRnRmTernaryOpSx(Context, () =>
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@ -1308,6 +1301,42 @@ namespace ChocolArm64.Instruction
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});
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});
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}
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}
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public static void Umin_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
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EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Uminp_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
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EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Umax_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Max), Types);
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EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Umaxp_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Max), Types);
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EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Umull_V(AILEmitterCtx Context)
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public static void Umull_V(AILEmitterCtx Context)
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{
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{
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
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@ -132,12 +132,12 @@ namespace ChocolArm64.Instruction
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if (SizeF == 0)
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if (SizeF == 0)
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{
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{
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Type = typeof(Sse);
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Type = typeof(Sse);
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BaseType = typeof(Vector128<float>);
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BaseType = typeof(Vector128<float>);
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}
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}
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else /* if (SizeF == 1) */
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else /* if (SizeF == 1) */
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{
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{
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Type = typeof(Sse2);
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Type = typeof(Sse2);
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BaseType = typeof(Vector128<double>);
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BaseType = typeof(Vector128<double>);
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}
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}
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@ -709,6 +709,46 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Op.Rd);
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Context.EmitStvec(Op.Rd);
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}
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}
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public static void EmitVectorPairwiseOpSx(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorPairwiseOp(Context, Emit, true);
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}
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public static void EmitVectorPairwiseOpZx(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorPairwiseOp(Context, Emit, false);
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}
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private static void EmitVectorPairwiseOp(AILEmitterCtx Context, Action Emit, bool Signed)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Half = Elems >> 1;
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for (int Index = 0; Index < Elems; Index++)
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{
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int Elem = (Index & (Half - 1)) << 1;
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EmitVectorExtract(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 0, Op.Size, Signed);
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EmitVectorExtract(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 1, Op.Size, Signed);
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Emit();
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void EmitScalarSet(AILEmitterCtx Context, int Reg, int Size)
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public static void EmitScalarSet(AILEmitterCtx Context, int Reg, int Size)
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{
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{
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EmitVectorZeroAll(Context, Reg);
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EmitVectorZeroAll(Context, Reg);
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@ -63,7 +63,7 @@ namespace ChocolArm64
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else
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else
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{
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{
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throw new ArgumentOutOfRangeException(nameof(Index));
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throw new ArgumentOutOfRangeException(nameof(Index));
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}
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}
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}
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}
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public static void EmitLdloc(this ILGenerator Generator, int Index)
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public static void EmitLdloc(this ILGenerator Generator, int Index)
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@ -89,7 +89,7 @@ namespace ChocolArm64
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throw new ArgumentOutOfRangeException(nameof(Index));
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throw new ArgumentOutOfRangeException(nameof(Index));
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}
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}
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break;
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break;
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}
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}
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}
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}
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public static void EmitStloc(this ILGenerator Generator, int Index)
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public static void EmitStloc(this ILGenerator Generator, int Index)
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@ -123,7 +123,7 @@ namespace ChocolArm64
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for (int Index = 0; Index < Count; Index++)
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for (int Index = 0; Index < Count; Index++)
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{
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{
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Generator.EmitLdarg(Index);
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Generator.EmitLdarg(Index);
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}
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}
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}
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}
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}
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}
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}
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}
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