diff --git a/AOpCodeTable.cs b/AOpCodeTable.cs
index e192f5e..5db495a 100644
--- a/AOpCodeTable.cs
+++ b/AOpCodeTable.cs
@@ -161,8 +161,10 @@ namespace ChocolArm64
             Set("000111100x10001xx10000xxxxxxxxxx", AInstEmit.Fcvt_S,        typeof(AOpCodeSimd));
             Set("x00111100x100100000000xxxxxxxxxx", AInstEmit.Fcvtas_Gp,     typeof(AOpCodeSimdCvt));
             Set("x00111100x100101000000xxxxxxxxxx", AInstEmit.Fcvtau_Gp,     typeof(AOpCodeSimdCvt));
+            Set("0x0011100x100001011110xxxxxxxxxx", AInstEmit.Fcvtl_V,       typeof(AOpCodeSimd));
             Set("x00111100x110000000000xxxxxxxxxx", AInstEmit.Fcvtms_Gp,     typeof(AOpCodeSimdCvt));
             Set("x00111100x110001000000xxxxxxxxxx", AInstEmit.Fcvtmu_Gp,     typeof(AOpCodeSimdCvt));
+            Set("0x0011100x100001011010xxxxxxxxxx", AInstEmit.Fcvtn_V,       typeof(AOpCodeSimd));
             Set("x00111100x101000000000xxxxxxxxxx", AInstEmit.Fcvtps_Gp,     typeof(AOpCodeSimdCvt));
             Set("x00111100x101001000000xxxxxxxxxx", AInstEmit.Fcvtpu_Gp,     typeof(AOpCodeSimdCvt));
             Set("x00111100x111000000000xxxxxxxxxx", AInstEmit.Fcvtzs_Gp,     typeof(AOpCodeSimdCvt));
diff --git a/Instruction/AInstEmitSimdCvt.cs b/Instruction/AInstEmitSimdCvt.cs
index 688f05a..e970277 100644
--- a/Instruction/AInstEmitSimdCvt.cs
+++ b/Instruction/AInstEmitSimdCvt.cs
@@ -31,6 +31,36 @@ namespace ChocolArm64.Instruction
             EmitFcvt_u_Gp(Context, () => EmitRoundMathCall(Context, MidpointRounding.AwayFromZero));
         }
 
+        public static void Fcvtl_V(AILEmitterCtx Context)
+        {
+            AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
+
+            int SizeF = Op.Size & 1;
+
+            int Elems = 4 >> SizeF;
+
+            int Part = Context.CurrOp.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
+
+            for (int Index = 0; Index < Elems; Index++)
+            {
+                if (SizeF == 0)
+                {
+                    //TODO: This need the half precision floating point type,
+                    //that is not yet supported on .NET. We should probably
+                    //do our own implementation on the meantime.
+                    throw new NotImplementedException();
+                }
+                else /* if (SizeF == 1) */
+                {
+                    EmitVectorExtractF(Context, Op.Rn, Part + Index, 0);
+
+                    Context.Emit(OpCodes.Conv_R8);
+                }
+
+                EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
+            }
+        }
+
         public static void Fcvtms_Gp(AILEmitterCtx Context)
         {
             EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Floor)));
@@ -41,6 +71,36 @@ namespace ChocolArm64.Instruction
             EmitFcvt_u_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Floor)));
         }
 
+        public static void Fcvtn_V(AILEmitterCtx Context)
+        {
+            AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
+
+            int SizeF = Op.Size & 1;
+
+            int Elems = 4 >> SizeF;
+
+            int Part = Context.CurrOp.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
+
+            for (int Index = 0; Index < Elems; Index++)
+            {
+                EmitVectorExtractF(Context, Op.Rd, Index, SizeF);
+
+                if (SizeF == 0)
+                {
+                    //TODO: This need the half precision floating point type,
+                    //that is not yet supported on .NET. We should probably
+                    //do our own implementation on the meantime.
+                    throw new NotImplementedException();
+                }
+                else /* if (SizeF == 1) */
+                {
+                    Context.Emit(OpCodes.Conv_R4);
+
+                    EmitVectorInsertF(Context, Op.Rd, Part + Index, 0);
+                }
+            }
+        }
+
         public static void Fcvtps_Gp(AILEmitterCtx Context)
         {
             EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Ceiling)));