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Add Sqxtun_S, Sqxtun_V with 3 tests. (#188)

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* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimd.cs
This commit is contained in:
LDj3SNuD 2018-06-26 04:36:20 +02:00 committed by gdkchan
parent 86aae79b9d
commit 31871077e2
1 changed files with 12 additions and 12 deletions
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24
Instruction/AInstEmitSimdArithmetic.cs
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@ -213,15 +213,15 @@ namespace ChocolArm64.Instruction
} }
} }
private static void EmitQxtn(AILEmitterCtx Context, bool Signed, bool Scalar) private static void EmitSaturatingExtNarrow(AILEmitterCtx Context, bool SignedSrc, bool SignedDst, bool Scalar)
{ {
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int Elems = (!Scalar ? 8 >> Op.Size : 1); int Elems = (!Scalar ? 8 >> Op.Size : 1);
int ESize = 8 << Op.Size; int ESize = 8 << Op.Size;
int TMaxValue = (Signed ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L)); int TMaxValue = (SignedDst ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
int TMinValue = (Signed ? -((1 << (ESize - 1))) : 0); int TMinValue = (SignedDst ? -((1 << (ESize - 1))) : 0);
int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0); int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0);
@ -233,14 +233,14 @@ namespace ChocolArm64.Instruction
AILLabel LblLe = new AILLabel(); AILLabel LblLe = new AILLabel();
AILLabel LblGeEnd = new AILLabel(); AILLabel LblGeEnd = new AILLabel();
EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed); EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
Context.Emit(OpCodes.Dup); Context.Emit(OpCodes.Dup);
Context.EmitLdc_I4(TMaxValue); Context.EmitLdc_I4(TMaxValue);
Context.Emit(OpCodes.Conv_U8); Context.Emit(OpCodes.Conv_U8);
Context.Emit(Signed ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe); Context.Emit(SignedSrc ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
Context.Emit(OpCodes.Pop); Context.Emit(OpCodes.Pop);
@ -258,7 +258,7 @@ namespace ChocolArm64.Instruction
Context.EmitLdc_I4(TMinValue); Context.EmitLdc_I4(TMinValue);
Context.Emit(OpCodes.Conv_I8); Context.Emit(OpCodes.Conv_I8);
Context.Emit(Signed ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd); Context.Emit(SignedSrc ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
Context.Emit(OpCodes.Pop); Context.Emit(OpCodes.Pop);
@ -1137,22 +1137,22 @@ namespace ChocolArm64.Instruction
public static void Sqxtn_S(AILEmitterCtx Context) public static void Sqxtn_S(AILEmitterCtx Context)
{ {
EmitQxtn(Context, Signed: true, Scalar: true); EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: true, Scalar: true);
} }
public static void Sqxtn_V(AILEmitterCtx Context) public static void Sqxtn_V(AILEmitterCtx Context)
{ {
EmitQxtn(Context, Signed: true, Scalar: false); EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: true, Scalar: false);
} }
public static void Sqxtun_S(AILEmitterCtx Context) public static void Sqxtun_S(AILEmitterCtx Context)
{ {
EmitQxtn(Context, Signed: false, Scalar: true); EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: false, Scalar: true);
} }
public static void Sqxtun_V(AILEmitterCtx Context) public static void Sqxtun_V(AILEmitterCtx Context)
{ {
EmitQxtn(Context, Signed: false, Scalar: false); EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: false, Scalar: false);
} }
public static void Sub_S(AILEmitterCtx Context) public static void Sub_S(AILEmitterCtx Context)
@ -1243,12 +1243,12 @@ namespace ChocolArm64.Instruction
public static void Uqxtn_S(AILEmitterCtx Context) public static void Uqxtn_S(AILEmitterCtx Context)
{ {
EmitQxtn(Context, Signed: false, Scalar: true); EmitSaturatingExtNarrow(Context, SignedSrc: false, SignedDst: false, Scalar: true);
} }
public static void Uqxtn_V(AILEmitterCtx Context) public static void Uqxtn_V(AILEmitterCtx Context)
{ {
EmitQxtn(Context, Signed: false, Scalar: false); EmitSaturatingExtNarrow(Context, SignedSrc: false, SignedDst: false, Scalar: false);
} }
} }
} }